Semiconductor device and its fabrication method

ABSTRACT

An electrically rewritable non-volatile memory device is configured by the EEPROM  3,  and an electrically non-rewritable non-volatile memory device is configured by the OTPROM  4   a.  Both the EEPROM  3  and the OTPROM  4   a  are configured by phase change memory devices each of which can be fabricated in the same fabrication step and at a low cost. The EEPROM 3  uses a phase change memory device in which an amorphous state and a crystal state of a phase change material are used for memory information, while the OTPROM  4   a  uses a phase change memory device in which a non-disconnection state and a disconnection state of a phase change material are used for memory information.

TECHNICAL FIELD

The present invention relates to a semiconductor device and itsfabrication method, and in particular to an effective technique appliedto a semiconductor device mounting non-volatile memory devices in amixed manner.

BACKGROUND ART

A semiconductor logic unit performs various operation processings undercontrol of a system program. When a scale of the system program islarge, an external memory device, for example, a magnetic disk, anoptical disk, or the like is used for a storage location for the systemprogram. When the scale of the system program is small, a non-volatilememory device fabricated on other substrate different from a substrateon which an operation processing section is formed for the storagelocation for the system program is used. One of typical examples of thenon-volatile memory device is a flash memory in which, for example, afloating-gate type device accumulating charges in an electrode or asilicon-nitride trapping device capturing charges in an insulation filmis used. Further, when the scale of the system program is small and itis necessary to reduce a size of the system itself, a non-volatilememory device fabricated on the same substrate on which the operationprocessing section has been formed for a storage location for the systemprogram is used. As a semiconductor logic unit including non-volatilememory devices on the same substrate in a mixed manner, there is, forexample, an IC (Integrated Circuit) card micro controller or an embeddedmicro controller.

In recent years, as one of memory cell techniques attracting attentionto a new electrically rewritable non-volatile memory device, there is aphase change memory device. The phase change memory device is a phasechange memory device in which chalcogenide used in, for example, CD-RW(Compact Disk Rewritable), DVD-RW (Digital Versatile Disk Rewritable),DVD-RAM (Digital Versatile Disk Random Access Memory) or the like, allof which are a rewritable optical memory medium, is applied to a memorydevice. The principle thereof is to utilize an amorphous state whereelectrical resistance is relatively high and a crystal state whereelectrical resistance is relatively low as memory information to readthe memory information as an electric signal, and rewriting of thememory information plural times is made possible. The amorphous stateand the crystal state are selectively produced by adjusting heatimparted to the memory device and a cooling rate of the memory device.That is, the amorphous state is formed by heating a phase changematerial up to a melted state thereof and the cooling it rapidly. Thecrystal state is formed by heating the phase change material up to themelted state thereof and then cooling it gradually or by maintaining aformed amorphous state at a crystallization temperature and then coolingit. Since the phase change memory device has such a merit that afabrication process thereof is simpler than that of a conventionalnon-volatile memory device such as a flash memory, and since a memorydevice itself can be made fine, fabrication thereof at a low cost isexpected.

For example, a phase change memory device in which a process temperatureis not restricted when being fabricated and fabrication thereof issimple, and its fabrication method have been disclosed (see PatentDocument 1, for example). A memory device structure in which a phasechange material in a phase change material memory device structure canbe more efficiently heated and a method for forming it have beendisclosed (see Patent Document 2, for example).

Patent Document 1: Japanese Patent Application Laid-open Publication No.2004-153047

Patent Document 2: Japanese Patent Application Laid-open Publication No.2003-332530

DISCLOSURE OF THE INVENTION

In the IC card micro controller, a system program is written in anon-volatile memory device under a wafer state or a chip state, and thena semiconductor logic unit including the non-volatile memory devices ina mixed manner is bonded to a card substrate in an adhesion process withheating. In the embedded micro controller, a system program is writtenin a non-volatile memory device in a state of being encapsulated statein a package, and then a semiconductor logic unit including thenon-volatile memory devices in a mixed manner is mounted on a circuitboard by soldering at a temperature of, for example, approximately 260°C. For that reason, it is required that the memory information stored inthe non-volatile memory device is not volatilized even if thenon-volatile memory device is subjected to heat in mounting. Forexample, in a conventional non-volatile memory device such as a flashmemory, the memory information is not lost by the above-mentioned heattreatment at the time of mounting.

However, in the phase change material constituting the phase changememory device, crystallization thereof progresses by heat. Thecrystallization of the phase change material is hard to occur for tenyears or more in an operating temperature range for a semiconductorproduct (approximately 0 to 85° C., for example). However, thecrystallization of the phase change material is progressed rapidlyduring a bonding process of the semiconductor logic unit to the cardsubstrate in the fabrication step of the above-mentioned IC card microcontroller or during soldering of the semiconductor logic unit to thecircuit board in the fabrication step of the embedded micro controller,and it is extremely difficult to prevent the crystallization. For thatreason, since there is such a possibility that the phase change memorydevice loses the memory information due to the above-mentioned heattreatment at the time of mounting, there is such a problem that thephase change memory device is hard to adapt to a fabrication step ofwriting the memory information before mounting. In view of thesecircumstances, the present inventors have studied avoidance of such aproblem that the memory information is lost due to the above-mentionedheat treatment during mounting by writing the memory information intothe phase change memory device after mounting, with using the phasechange memory device only for a non-volatile memory device whichrequires rewriting of the memory information and stores specific memoryinformation.

However, since the phase change memory device can be fabricated at a lowcost, it is desired to use the phase change memory device for anon-volatile memory device which does not require rewriting of thememory information. In the phase change memory device used for such anapplication, since rewriting of the memory information is not required,it is preferable that writing of the memory information into the phasechange memory device is performed before mounting rather than aftermounting. However, as described above, when the memory information iswritten into the phase change memory device before mounting, there issuch a problem that the memory information is lost by the heat treatmentat the time of mounting.

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

A semiconductor device according to the present invention comprises anelectrically rewritable first non-volatile memory device, and anelectrically non-rewritable second non-volatile memory device on thesame semiconductor substrate, wherein the first non-volatile memorydevice is configured by a first phase change memory device capable ofrewriting the memory information plural times, and the secondnon-volatile memory device is configured by a second phase change memorydevice capable of writing the memory information only one time, andinformation holding sections of the first and second phase change memorydevices have the same structure.

A fabrication method of a semiconductor device according to the presentinvention comprises the steps of: forming a first field effecttransistor of a low withstand voltage system on an electricallyrewritable first non-volatile memory device formation region, andforming a second field effect transistor of a high withstand voltagesystem on an electrically non-rewritable second non-volatile memorydevice formation region, by a unit of one chip on a semiconductor wafer;respectively forming phase change materials electrically connected todrain regions of the first and second field effect transistors, forminga first phase change memory device comprising the first field effecttransistor and the phase change material on the first non-volatilememory device formation region, and forming a second phase change memorydevice comprising the second field effect transistor and the phasechange material on the second non-volatile memory device formationregion; inspecting a semiconductor device including the firstnon-volatile memory device and the second non-volatile memory device onthe semiconductor wafer by a unit of one chip, and simultaneouslywriting the memory information in the second phase change memory device;and rewriting the memory information of the first phase change memorydevice after mounting an individual chip obtained by cutting thesemiconductor wafer on a mounting substrate.

An effect obtained by typical ones of the inventions disclosed in thepresent application will be briefly described below.

A semiconductor device can be fabricated at a low cost.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a circuit block diagram of a semiconductor logic unitaccording to a first embodiment;

FIG. 2 is a block diagram of an integrated circuit of the semiconductorlogic unit according to the first embodiment;

FIG. 3A is a configuration diagram of a first phase change memory deviceused in an EEPROM according to the first embodiment, and FIG. 3B is aschematic view of a cross sectional structure of an information holdingsection of the first phase change memory device;

FIG. 4 is a graph showing current-voltage characteristics of the phasechange material according to the first embodiment;

FIG. 5A is a configuration diagram of a second phase change memorydevice used in an OTPROM according to the first embodiment, FIG. 5B is aschematic view of a cross sectional structure of an information holdingsection in a high resistance state in the second phase change memorydevice, and FIG. 5C is a graph showing a relationship between atemperature and a biased time of a voltage in a phase change material;

FIG. 6 is a circuit configuration diagram of the OTPROM according to thefirst embodiment;

FIG. 7 is a planer layout diagram of the OPROM corresponding to thecircuit configuration shown in FIG. 6;

FIG. 8 is a circuit configuration diagram of an EEPROM according to thefirst embodiment;

FIG. 9 is a planer layout diagram of the EEPROM corresponding to thecircuit configuration shown in FIG. 8;

FIG. 10 is a sectional view of a principal part of a semiconductorsubstrate showing a fabrication step of the semiconductor logic unitaccording to the first embodiment;

FIG. 11 is a sectional view of a principal part of a semiconductorsubstrate showing the fabrication step of the semiconductor logic unitaccording to the first embodiment;

FIG. 12 is a sectional view of a principal part of the semiconductorsubstrate showing the fabrication step of the semiconductor logic unitaccording to the first embodiment;

FIG. 13 is a schematic view showing the fabrication step of an IC cardaccording to the first embodiment;

FIG. 14 is a schematic view showing the fabrication step of an IC cardaccording to the first embodiment;

FIG. 15 is a schematic view showing the fabrication step of an IC cardaccording to the first embodiment;

FIG. 16 is a schematic view showing the fabrication step of an IC cardaccording to the first embodiment;

FIG. 17 is a schematic view of a cross sectional structure of aninformation holding section of a third phase change memory deviceaccording to a second embodiment;

FIG. 18 is a graph showing a relationship between electrical resistanceof the third phase change memory device used in the OTPROM and aset-reset cycle of information according to the second embodiment;

FIG. 19 is a sectional view of a principal part of a semiconductorsubstrate showing the third phase change memory device and a peripheralcircuit low withstand voltage system nMIS used in the OTPROM accordingto the second embodiment; and

FIG. 20 is a block diagram of an integrated circuit of a semiconductorlogic unit according to the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

In the embodiments, the invention will be described in a plurality ofthe sections or embodiments when required as a matter of convenience.However, these sections or embodiments are not irrelevant to each otherunless otherwise stated, and the one relates to the entire or a part ofthe other as a modification example, details, or a supplementaryexplanation thereof.

Also, in the embodiments described, when referring to the number ofelements (including number of pieces, values, amount, range, and thelike), the number of the elements is not limited to a specific numberunless otherwise stated or except the case where the number isapparently limited to a specific number in principle. The number largeror smaller than the specified number is also applicable. Further, in theembodiments described, it goes without saying that the components(including element steps) are not always indispensable unless otherwisestated or except the case where the components are apparentlyindispensable in principle. Similarly, in the embodiments describedbelow, when the shape of the components, positional relation thereof,and the like are mentioned, the substantially approximate and similarshapes and the like are included therein unless otherwise stated orexcept the case where it can be conceived that they are apparentlyexcluded in principle. The same goes for the numerical value and therange described above.

In the embodiments, MISFET (Metal Insulator Semiconductor Field EffectTransistor) representing a field effect transistor is abbreviated asMIS. In the embodiments, when referring to a wafer, it mainly representsa Si monocrystalline wafer, but it does not indicate only the same andit indicates an SOI (Silicon ON Insulator) wafer, an insulation filmsubstrate on which an integrated circuit is formed, or the like.

Also, components having the same function are denoted by the samereference symbols throughout the drawings for describing theembodiments, and the repetitive description thereof is omitted.

First Embodiment

A semiconductor logic unit according to a first embodiment will bedescribed with reference to FIG. 1 to FIG. 16.

In FIG. 1, a circuit block diagram of a semiconductor logic unitaccording to the first embodiment is shown. A semiconductor logic unitLC is configured by a central processing unit (CPU) 1 performingoperation, a volatile memory device LC1, and a non-volatile memorydevice LC2. In the volatile memory device LC1, for example, RAM (RandomAccess Memory) 2 typified by SRAM (Static Random Access Memory) isformed, while in the non-volatile memory device LC2, for example, EEPROM(Electrically Erasable Programmable Read Only Memory) 3 rewritable ofinformation and a ROM (Read Only Memory) 4 non-rewritable of informationonly for reading are formed. In the ROMs 4, for example, an OTPROM (OneTime Programming Read Only Memory) 4 a and a masked ROM (Masked ReadOnly Memory) 4 b are formed. Also, phase change memory devices are usedin the EEPROM 3 and the OTPROM 4 a formed in the non-volatile memorydevice LC2.

In general, variation in performance of the semiconductor logic units LCis generated in the fabrication step. Therefore, it is necessary tostore voltage selecting information, circuit constant adjustinginformation, or the like for each of the semiconductor logic units LC.These information items can not be determined at the time of a productdesigning, and they are written into a portion of the EEPROM 3 afterfabricating the semiconductor logic unit LC (after mounting thesemiconductor logic unit LC on an IC card, for example, in the firstembodiment).

In FIG. 2, a block diagram of an integrated circuit of the semiconductorlogic unit according to the first embodiment is shown. In addition tothe above-mentioned central processing unit 1, volatile memory deviceLC1, and non-volatile memory device LC2, an input/output circuit IO,input circuits IO1, IO2, and a booster circuit CP are disposed in thesemiconductor logic unit LC. Address ADD, write data WDATA, read controlRE, and read data RDATA are inputted from the central processing unit 1to a memory module MM1 configured by the RAM 2 and the EEPROM 3, and toa one-time-programming-memory module MM2 configured by the OTPROM 4 aand the masked ROM 4 b. The write control WE is inputted from thecentral processing unit 1 only to the memory module MM1. Further, avoltage VDD 1 (for example, 10 V) is inputted from the booster circuitCP into the one-time-programming-memory module MM2, a voltage VDD2 (forexample, 6 V) is inputted from the input circuit IO1 thereinto, and aone-time-programming-memory-write-control signal OWE is inputted fromthe input circuit IO2 thereinto. Reading from the one-time-programmingmodule MM2 is performed by the central processing unit 1, and writingtherein is performed by a tester or the like.

Phase change memory devices are used as memory cells in the EEPROM 3 andthe OTPROM 4 a. The phase change memory device can be fabricated at acost lower than that of such a carrier-trapping type non-volatile memorydevice such as a floating-gate type non-volatile memory device or MONOS(Metal Oxide Nitride Oxide Semiconductor). Therefore, an inexpensivesemiconductor logic unit LC can be provided by using the phase changememory devices for the EEPROM 3 and the OTPROM 4 a.

In the present invention, a first phase change memory device used in theEEPROM 3 and a second phase change memory device used in the OTPROM 4 aare characterized by that their information storing methods,applications or the like are different from each other, although theirinformation holding sections have the same basic structure. That is, theinformation holding section of the first phase change memory device usedin the EEPROM 3 utilizes a difference in electrical resistance betweenthe amorphous state and the crystal state of the phase change materialfor the memory information, while the information holding section of thesecond phase change memory device used in the OTPROM 4 a utilizes adifference in electrical resistance between a non-disconnection stateand a disconnection state of the phase change material for the memoryinformation. Further, in the case of the first phase change memorydevice used in the EEPROM 3, writing of the memory information isperformed after mounting the semiconductor logic unit LC on, forexample, an IC card. In the case of the second phase change memorydevice used in the OTPROM 4 a, writing of the memory information isperformed before mounting the semiconductor logic unit LC on, forexample, an IC card.

The information holding section of the first phase change memory deviceused in the EEPROM 3 and the information holding section of the secondphase change memory device used in the OTPROM 4 a will be described indetail below.

FIG. 3A is a configuration diagram of the first phase change memorydevice used in the EEPROM according to the first embodiment, and FIG. 3Bis a schematic view of a cross-sectional structure of the informationholding section of the first phase change memory device.

As shown in FIG. 3A, a phase change memory device 10 is configured by aselection nMIS 10 a and an information holding section 10 b. Here,MISFET is exemplified as a device functioning as a switch, but a bipolartransistor or a diode may be used.

As shown in FIG. 3B, the information holding section 10 b has astructure in which a phase change material 11 and an upper electrode 12stacked thereon are disposed between a first wiring layer 13 and asecond wiring layer 14. The first wiring layer 13 positioned at a lowerlayer and the phase change material 11 are electrically connected toeach other via a first plug 15. The second wiring layer 14 positioned atan upper layer and the upper electrode 12 are electrically connected toeach other via a second plug 16. The phase change material 11 iscomposed of inorganic material such as, for example, Ge—Sb—Te alloy orAg—In—Te alloy, and a thickness thereof is approximately 100 nm, forexample. The upper electrode 12, the first wiring layer 13, and thesecond wiring layer 14 are composed of electrically conductive materialcontaining Al as a main component, for example.

By carrying a current between the first wiring layer 13 and the secondwiring layer 14, joule heat is generated on a side near the first plug15 or in the first plug itself to change the phase change material 11from the amorphous state to the crystal state or from the crystal stateto the amorphous state.

FIG. 4 is a graph showing current-voltage characteristics of the phasechange material according to the first embodiment (a voltage measured bysweeping the current).

For example, when a current source 17 is connected to the second wiringlayer 14 positioned at the upper layer with the information holdingsection 10 b shown in FIG. 3B and sweeping of the current in which thecurrent is gradually increased from an initial state is performed, aregion, which a voltage rises rapidly at a certain current value,appears. Thereafter, even if sweeping of the current for decreasing thecurrent is performed, the voltage does not return back to a low voltageof the initial state, so that electrical resistance of the phase changematerial 11 remains in an extremely high state, namely, an insulatedstate. In the information holding section of the phase change memorydevice used in the OTPROM 4 a, the disconnection state and thenon-disconnection state are used for the memory information.

FIG. 5A is a configuration diagram of the second phase change memorydevice used in the OTPROM according to the first embodiment, FIG. 5B isa schematic view of a cross sectional structure of the informationholding section of the second phase change memory device in a highresistance state, and FIG. 5C shows a relationship between a temperatureof the phase change material and a biased time of the voltage.

As shown in FIG. 5A, the second phase change memory device 18 isconfigured by a selection nMIS 18 a and an information holding section18 b. Here, MISFET is exemplified as a device functioning as a switch,but a bipolar transistor or a diode may be used.

As shown in FIG. 5B, a basic structure of the information holdingsection 18 b is the same structure as the information holding section 10b of the first phase change memory device 10 used in the above-mentionedEEPRPM 3. However, in the information holding section 18 b in a highresistance state, a cavity 19 with a height of approximately 20 to 30 nmis formed in a portion of the phase change material 11 contacting withan upper portion of the first plug 15. As a result, the phase changematerial 11 and the upper portion of the first plug 15 are disconnectedfrom each other, so that the information holding section 18 b in a highresistance state can be obtained.

When rewriting of the memory information is performed in the informationholding section 10 b of the first phase change memory device 10 used inthe EEPROM 3, the amorphous state is formed, for example, by heating thephase change material 11 up to a melted state and then cooling itrapidly. Change in a temperature of the phase change material when thephase change material 11 becomes amorphous is represented by the line“a” in FIG. 5C. The crystal state is formed, for example, by maintainingthe amorphous state of the phase change material 11 at a crystallizationtemperature and then cooling the phase change material 11. Change in atemperature of the phase change material when the phase change material11 is crystallized is represented by the line “b” in FIG. 5C. In bothcases, the cavity 19 is not formed in the phase change material 11.Incidentally, the crystal state can also be formed, for example, byheating the phase change material 11 up to a melted state and thencooling it gradually.

On the other hand, when a relatively large voltage is applied to theinformation holding section 18 b of the second phase change memorydevice 18 used in the OTPROM 4 a or a relatively large current is passedtherethrough, as represented by the line “c” in FIG. 5C, the phasechange material 11 has a temperature higher than the case that rewritingof the memory information is performed in the information holdingsection 10 b of the first phase change memory device 10 (the line “a” orthe line “b” in FIG. 5C). It is thought that the cavity 19 is formed inthe portion of the phase change material 11 contacting with the upperportion of the first plug 15 due to the high temperature. That is, it isthought that the cavity 19 is formed, for example, by cooling the phasechange material 11 in a state where the phase change material 11 isexfoliated from an upper face of the first plug 15 after the phasechange material 11 is melted and its volume is expanded, or bysublimation of the phase change material 11.

The phase change material 11 has a behavior that crystallization occursby heat, so that the memory information which has been stored in a highresistance state with amorphous state is lost. However, since the highresistance state can be created by applying a relatively large voltageto the phase change material 11 or carrying a relatively high currentthereinto, it is possible to use the second phase change memory deviceas a memory cell for a heat-resisting non-volatile memory device inwhich the memory information does not change even at a temperature of,for example, 260° C. When this usage is adopted, just one electricalwriting can be allowed, but the memory information can be held evenafter mounting the memory device on, for example, an IC card.

Next, the OTPROM according to the first embodiment will be describedwith reference to a circuit configuration diagram shown in FIG. 6.

A memory array MARY constituting the OTPROM is configured by a pluralityof word lines and a plurality of bit lines. For example, a second phasechange memory device CEL11 is connected to an intersection between aword line WL1 and a bit line BL1. Each second phase change memory deviceis configured by a selection nMIS and an information holding section.The information holding section has, for example, a low resistance ofapproximately 1 KΩ to 10 KΩ when the phase change material is in thenon-disconnection state and has a high resistance of 100 KΩ or more whenthe phase change material is in a disconnection state, for example. Agate electrode of the selection nMIS (MN11) is connected with the wordline WL1. When the selection nMIS (MN11) is selected, the gate electrodeis made to be in a positive voltage, and when is not selected, it ismade to be in 0 V, and therefore, control is performed so that theselection nMIS (MN11) is made to be in an ON state or an OFF statecorrespondingly. One terminal of the second phase change memory deviceCEL11 is connected to the bit line BL1 and the source electrode of theselection nMIS (MN11) is connected to a ground potential.

A word driver circuit WD1 is connected to the word line WL1. Forexample, the word driver circuit WD1 is configured by a pMIS (MP1) andan nMIS (MN1). Since a source electrode of the pMIS (MP1) is appliedwith a voltage VDD1 of, for example, 10 V, the pMIS (MP1) and the nMIS(MN1) are made to be a high withstand voltage MIS. Groups of the worddriver circuits WD1, WD2, . . . are arranged in a longitudinal directionto form a word driver block WDARY. An X system address decoder blockADEC is disposed adjacent to the word driver block WDARY.

A column selection circuit YS1 is connected to the bit line BL1. The bitline BL1 is connected to the pMIS (MP31) and is selectively connected toa sense amplifier SA by a control signal YSR1. The control signal YSR1is supplied from a control circuit CNTL. An amplifier array AMPARY isconfigured by the sense amplifier SA and a pre-charge circuit PCR. Thesense amplifier SA amplifies a signal of the bit line BL1 activated byan activating signal. The pre-charge circuit PCR is configured by a pMIS(MP40) and is controlled by a pre-charge control signal PC to supply aread voltage Vr to the bit line BL1. A write Y switch array WYSARY isconfigured by a high withstand voltage pMIS, and the gate electrodethereof is connected to a control signal YSW1 and a source electrodethereof is applied with a voltage VDD2 of, for example, 6 V. The controlsignal YSW1 is controlled by a write address decoder WADEC.

Since the second phase change memory devices CEL11, CEL12, . . . ,CEL21, CEL22, . . . of the OTPROM are applied with a high voltage, phasechange materials PCM11, PCM12, . . . , PCM21, PCM22, . . . and selectionnMIS (MN11, MN12, . . . , MN21, MN22, . . . ) connected the phase changematerial in series are required to have corresponding withstandvoltages. In this example, a voltage of 10 V is applied to the wordlines WL1, WL2, . . . , and a voltage of 6 V is applied to the bit linesBL1, BL2, . . . , so that the phase change material of a desired secondphase change memory device is insulated. Therefore, MIS of a highwithstand voltage system having a withstand voltage of at least 10 V ormore is required in order to conduct a normal operation. MIS of a highwithstand voltage system described in FIG. 6 includes pMIS (MP1, MP2,MP21, MP22) and nMIS (MN1, MN2, MN11, MN12, MN21, MN22).

In FIG. 7, a planer layout diagram of the OTPROM corresponding to thecircuit configuration of the above-mentioned FIG. 6 is shown. In FIG. 7,the eight second phase change memory devices are positioned atintersections between the word lines WL1 to WL4 and the bit lines BL1and BL2 are shown.

A device isolation SGI is, for example, a shallow trench type, and isgenerally used for a semiconductor device. A second phase change memorydevice is positioned at an intersection between the word line WL1 andthe bit line BL1. The second phase change memory device is configured bya selection nMIS and a phase change material PCM01. A common source lineSL is a wiring layer connected to a source region of the selection nMISdisposed for each second phase change memory device. The phase changematerial PCM01 is connected to a drain region of the selection RMIS viaa lower plug BM01, a first wiring layer M1, and a first plug PLUG1.Further, the phase change material PCM01 is connected to the bit lineBL1 via a second plug PLUG2. A gate length of the selection nMIS isformed to be longer than, for example, a gate length of MIS used in corelogic on the same substrate so as to withstand a high voltage. Inaddition, since a high withstand voltage MIS has generally poor drivingability, a gate width of the selection nMIS is formed to be wide, whichallows carrying of a large amount of current. In this case, in order todeal with increase in the current, the number of contact holes formed soas to contact with the source region of the selection nMIS is alsoincreased.

As described above, the phase change material PCM01 is disconnected tobe in a permanent high resistance state by turning ON the selection nMISby applying, for example, 6 V to the bit line BL1 and applying, forexample, 10 V to the word line WL1. That is, the second phase changememory device has a structure capable of electrically writing the memoryinformation therein, and accordingly the memory information can beeasily written in the second phase change memory device via an existingtester. Incidentally, voltages applied to the bit line BL1 and the wordline WL1 at this time are only one example and other voltages can beused if a combination thereof can disconnect the phase change materialPCM01.

Next, the EEPROM according to the first embodiment will be describedwith using a circuit configuration diagram shown in FIG. 8. A basicstructure of the information holding section is the same structure asthe OTPROM (see the above-mentioned FIG. 6) previously explained, butsince writing with breakdown of the phase change material is notperformed in the EEPROM, the selection nMIS of a high withstand voltagesystem used in the above-mentioned FIG. 6 is not used. Here, EEPROM,which performs rewriting and reading at a voltage of 1.5 V or less aswith MIS used in core logic, is exemplified.

A memory array MARYL constituting the EEPROM is configured by aplurality of word lines and a plurality of bit lines. A first phasechange memory device is connected to an intersection between each wordline and each bit line. For example, a first phase change memory deviceCEL11L is disposed at an intersection between a word line WL1L and a bitline BL1L. Each first phase change memory device is configured by aselection nMIS and an information holding section. The informationholding section has, for example, a low resistance of approximately 1 KΩto 10 KΩ when the phase change material is in a crystal state, and has ahigh resistance of 100 KΩ or more when the phase change material is inan amorphous state. A gate electrode of the selection nMIS (MN11L) isconnected with the word line WL1L. When the selection nMIS (MN11L) isselected, the gate electrode is made to be in a positive voltage, andwhen is not selected, it is made to be in 0 V, and therefore, control isperformed so that the selection nMIS (MN11L) is made to be in an ONstate or an OFF state correspondingly. One terminal of the phase changememory device CEL11L is connected to the bit line BL1L and the sourceelectrode of the selection nMIS (MN11L) is connected to a groundpotential.

A word driver circuit WD1L is connected to the word line WL1L. Forexample, the word driver circuit WD1L is configured by pMIS (MP1L) for1.5 V and nMIS (MN1L) for 1.5 V. The source electrode of the pMIS (MP1L)is applied with a voltage VDD3 of, for example, 1.5 V. Groups of theseword driver circuits WD1L, WD2L, . . . , are arranged in a longitudinaldirection to form a word driver block WDARYL. An X system addressdecoder block ADECL is disposed adjacent to the word driver blockWDARYL.

A column selection circuit YS1L is connected to the bit line BL1L. Forexample, the bit line BL1L is connected with pMIS (MP31L), and it isselectively connected to a sense amplifier SAL by a control signalYSR1L. The control signal YSR1L is supplied from a control circuitCNTLL. An amplifier array AMPARYL is configured by a sense amplifier SALand a pre-charge circuit PCRL. The sense amplifier SAL amplifies asignal on the bit line BL1L or the bit line BL2L activated by anactivating signal. The pre-charge circuit PCRL is configured by pMIS(MP40L), and is controlled by a pre-charge control signal PCL to supplya read voltage VrL to the bit line BL1. A write Y switch array WYSARYLis configured by high withstand voltage pMIS (MP21L, MP22L) and thelike, a gate electrode thereof is connected with a control signal YSW1L,and a source electrode thereof is applied a with voltage VDD4 of, forexample, 1.5 V. The control signal YSW1L is controlled by a writeaddress decoder WADECL. The EEPROM 3 is different from the OTPROM 4 a,and rewrite therein is performed with a voltage of 1.5 V or lower.Therefore, the first phase change memory device including selection MISof a low withstand voltage system can be used in the EEPROM.

In FIG. 9, a planer layout diagram of the EEPROM corresponding to thecircuit configuration of the above-mentioned FIG. 8 is shown. In FIG. 9,the 20 first phase change memory devices positioned at intersectionsbetween the word lines WL1L to WL4L and the bit lines BL1L to BL5L areshown.

A device isolation SGI is, for example, a shallow trench type, and isgenerally used for a semiconductor device. The first phase change memorydevice is positioned at an intersection between the word line WL1L andthe bit line BL1L. The first phase change memory device is configured bythe selection nMIS and the phase change material PCM01L. A common sourceline SLL is a wiring layer connected to a source region of the selectionnMIS disposed for each first phase change memory device. The phasechange material PCM01L is connected to a drain region of the selectionnMIS via a lower plug BM01L, a first wiring layer M1L, and a first plugPLUG1L. Further, the phase change material PCM01L is connected to thebit line BL1L via a second plug PLUG2L. A gate length of the selectionnMIS is, for example, the same as a gate length of MIS used in a corelogic on the same substrate. An integration degree of the first phasechange memory device is required, so that a gate width of the selectionnMIS constituting the first phase change memory device is narrower thana gate width of the selection nMIS constituting the second phase changememory device of the OTPROM. Accordingly, the number of contact holesformed on the first phase change memory device of the EEPROM can be lessthan the number of contact holes formed on the second phase changememory device of the OTPROM. Rewriting and reading are performed at avoltage of 1.5 V or lower.

Next, one example of a fabrication method of the semiconductor logicunit according to the first embodiment will be described with referenceto a sectional views of a principal part of a semiconductor substrateshown in FIGS. 10 to 12. In these figures, the second phase changememory device and a peripheral circuit low withstand voltage system nMISare described. However, the other devices, for example, a peripheralcircuit low withstand voltage system pMIS, peripheral circuit highwithstand voltage systems nMIS and pMIS, and the like are omitted.

First, as shown in FIG. 10, a device isolation 52 of a shallow trenchtype is formed in a device isolation region on a main surface of asemiconductor substrate which is composed of, for example,monocrystalline silicon of p type (a thin plate of semiconductor with anapproximately circular shape in plan called “semiconductor wafer” inthis stage) 51. Then, a predetermined impurity is selectively introducedwith predetermined energy by ion implantation, whereby an n-well 53 m isformed on a second phase change memory device formation region, and ann-well 53 are formed on a peripheral circuit low withstand voltagesystem nMIS formation region.

Next, for example, an insulation film 54 with a thickness ofapproximately 8 nm and an insulation film 54 m with a thickness ofapproximately 20 nm are formed on the main surface of the semiconductorsubstrate 51. The insulation film 54 constitutes a gate insulation filmof the peripheral circuit low withstand voltage system nMIS, while theinsulation film 54 m constitutes a gate insulation film of the selectionnMIS of the second phase change memory device.

Next, for example, after a conductor film composed of low-resistivepolysilicon with a thickness of approximately 100 nm is formed on themain surface of the semiconductor substrate 51, the conductive film isprocessed by etching with a photo-resist pattern as a mask to form agate electrode 55 of the peripheral circuit low withstand voltage systemnMIS and a gate electrode 55 m of the selection nMIS. Subsequently, apair of n-type diffusion layers with a relatively low impurityconcentration, which constitute a part of a source and drain of theperipheral circuit low withstand voltage system nMIS and the selectionnMIS, is formed. Side-walls 56 are formed on side walls of the gateelectrode 55 of the peripheral circuit low withstand voltage system nMISand the gate electrode 55 m of the selection nMIS. Further, a pair ofn-type diffusion layers with a relatively high impurity concentration,which constitute other part of the source and drain of the peripheralcircuit low withstand voltage system nMIS and the selection nMIS, isformed. Whereby, a source region LS and a drain region LD of theperipheral circuit low withstand voltage system nMIS, and a sourceregion HS and a drain region HD of the selection nMIS are formed.Incidentally, the source region HS and the drain region HD of theselection nMIS are distant from an end of the gate electrode 55 m, sothat a structure for improving a voltage withstand is made.

Next, a low resistance layer 57 composed of alloy of high melting pointmetal and silicon is formed on the gate electrode 55, the source regionLS, and the drain region LD of the peripheral circuit low withstandvoltage system nMIS, and on the gate electrode 55 m, the source regionHS, and the drain region HD of the selection nMIS, by salicidation(self-aligned silicidation) technique.

Next, after a first interlayer insulator film 58 composed of, forexample, silicon oxide is formed on the main surface of thesemiconductor substrate 51, the first interlayer insulator film 58 isprocessed by etching with a photo-resist pattern as a mask to formcontact holes C1 so as to expose a part of the semiconductor substrate51 (for example, the source region LS and the drain region LD of theperipheral circuit low withstand voltage system nMIS, and the sourceregion HS and the drain region HD of the selection nMIS), a part of thegate electrode 55 of the peripheral circuit low withstand voltage systemnMIS, and a part of the gate electrode 55 m of the selection nMIS.

next, after a TiN (titanium nitride) film and a W (tungsten) film, forexample, are sequentially deposited on the main surface of thesemiconductor substrate 51 in order from a lower layer, plugs 59 areformed inside the contact holes C1 by polishing these metal films by CMP(Chemical Mechanical Polishing) method so that the metal films are leftonly in the contact holes C1. Then, after an Al alloy film and a TiNfilm, for example, are sequentially deposited on the main surface of thesemiconductor substrate 51 in order from a lower layer, these metalfilms are processed by etching with a photo-resist pattern as a mask toform a first wiring layer M1. Thereafter, a second interlayer insulatorfilm 60 composed of, for example, silicon oxide is formed on the mainsurface of the semiconductor substrate 51.

Next, as shown in FIG. 11, the second interlayer insulator film 60 isprocessed by etching with a photo-resist pattern as a mask to form thePLUG1 in which a part of the first wiring layer M1 is exposed. Then,after a TiN film and a W film, for example, are sequentially depositedon the main surface of the semiconductor substrate 51 in order from alower layer, the plug 61 is formed inside the PLUG1 by polishing thesemetal films by CMP (Chemical Mechanical Polishing) method so that themetal films are left only in the PLUG1.

Next, inorganic material composed of alloy of Ge, Sb, Sn, Se, Zn, Co,Te, or the like is deposited on the main surface of the semiconductorsubstrate 51, and then a metal film of Al, Au, Cu, Ag, Mo, Ti, W, Ta, orthe like is further deposited thereon. Thereafter, the metal film andthe inorganic material are sequentially processed by etching with aphoto-resist pattern as a mask so that a phase change material 62composed of the inorganic material and an upper electrode 63 composed ofthe metal film are formed. Subsequently, a third interlayer insulatorfilm 64 composed of, for example, silicon oxide is formed on the mainsurface of the semiconductor substrate 51.

The second phase change memory device used in the OTPROM comprises acombination of the selection nMIS of a high withstand voltage system andthe information holding section. A gate length of the gate electrode 55m of the selection nMIS of the second phase change memory device shownin FIG. 11 is longer than a gate length of the gate electrode of MISused in a core logic. Also, a thickness of the gate insulator film 54 mof the selection nMIS of the second phase change memory device isthicker than a thickness of the gate insulator film of the gateelectrode of MIS used in the core logic. The reason for this is that,for example, a voltage of 10 V, which is higher than, for example, avoltage 1.5 V applied to the gate electrode of MIS used in the corelogic, is used in the selection nMIS of the second phase change memorydevice used in the OTPROM. Incidentally, when the first phase changememory device is used in the EEPROM, a configuration in which the phasechange material is connected to the MIS used in the core logic can beadopted, so that an area of the first phase change memory device can bereduced.

Next, as shown in FIG. 12, the third interlayer insulator film 64 isprocessed by etching with a photo-resist pattern as a mask to formthrough-holes TH2 in which a part of the upper electrode 63 is exposed.Then, after an Al alloy film and a TiN film, for example, aresequentially deposited on the main surface of the semiconductorsubstrate 51 in order from a lower layer, these metal films areprocessed by etching with a photo-resist pattern as a mask to form asecond wiring layer M2. Thereafter, a fourth interlayer insulator filmINS4 composed of, for example, silicon oxide is formed on the mainsurface of the semiconductor substrate 51. Whereby, the second phasechange memory device comprising the selection nMIS and the informationholding section is substantially formed.

Here, the fabrication method of the second phase change memory devicewhich is used in the OTPROM and configured by a combination of theselection nMIS of the high withstand voltage system and the informationholding section using the disconnection state and the non-disconnectionstate of the phase change material, has been described. However, thefirst phase change memory device which is used in the EEPROM andconfigured by a combination of the selection nMIS of the low withstandvoltage system and the information holding section using the amorphousstate and the crystal state of the phase change material, is similarlyformed. That is, since the number of fabrication steps of EEPROM is notincreased due to provision of the OTPROM, the semiconductor logic unitcan be fabricated at a low cost.

Next, steps of mounting the semiconductor logic unit according to thefirst embodiment on the IC card will be described with reference to FIG.13 to FIG. 16.

FIG. 13 is a diagram in which a plurality of semiconductor logic unitsis formed on a main surface of a semiconductor wafer WAFER.Semiconductor devices are formed on the semiconductor wafer WAFER by aunit of one chip CHIP, for example, according to fabrication stepsdescribed with reference to the above-mentioned FIG. 10 to FIG. 12.

FIG. 14 is a diagram showing an inspection step of each of semiconductorlogic units. The semiconductor wafer WAFER is placed on a measuringstage. Then, while a probe is made to contact with an electrode pad ofthe semiconductor logic unit to input a signal waveform from an inputterminal, a signal waveform is outputted from an output terminal.Inspection whether or not each of the semiconductor logic units operatesnormally is conducted by reading the outputted signal waveform with anequipment such as a tester TES. At this time, the memory information iswritten in the OTPROM of each of the semiconductor logic units. That is,in the case where the memory information is stored in the OTPROM, an onetime programming memory writing control signal OWE is inputted to abonding pad connected to the input circuit IO2 shown in FIG. 2 from thetester so that an operation mode of the semiconductor logic unit ischanged to a writing mode for the OPTROM, whereby writing is madepossible.

FIG. 15 is a diagram showing a cutting step of cutting the semiconductorwafer WAFER into individual chips CHIP. Incidentally, writing in theOTPROM can be performed after the cutting step.

FIG. 16 is a diagram showing a bonding step of bonding the chip CHIP toa plastic card case CSE. At this time, a heat of a temperature of, forexample, approximately 200° C. is applied for the bonding process, butinformation previously written in the second phase change memory deviceof the OTPROM is not erased. Further, after the chip CHIP is mounted onthe plastic card case CSE, the memory information is electricallywritten into the EEPROM.

Note that, in the first embodiment, the case where the semiconductorlogic unit LC is mounted on the IC card has been described, but thesemiconductor logic unit LC can be mounted on an embedded microcontroller or the like.

As described above, according to the first embodiment, an electricallyrewritable non-volatile memory device is configured by the EEPROM 3, andan electrically non-rewritable non-volatile memory device is configuredby the OTPROM 4 a. The first and second phase change memory devices eachof which can be fabricated at the same fabrication step and at a lowcost are used in both the EEPROM 3 and the OTPROM 4 a, respectively.Whereby, the semiconductor logic unit in which the electricallyrewritable non-volatile memory device and the electricallynon-rewritable non-volatile memory device are mounted on the samesubstrate can be fabricated at a low cost. Further, an inexpensive ICcard can be provided by mounting the semiconductor logic unit fabricatedat a low cost. Incidentally, in the second phase change memory deviceconstituting the OTPROM 4 a, the non-disconnection state or thedisconnection state in which the memory information is not lost even ifheat treatment at a temperature of approximately 260° C. is performedthereto is used as the memory information. Whereby the memoryinformation written in the OTPROM 4 a is not lost even if thesemiconductor logic unit mounting the OTPROM 4 a thereon is mounted onan IC card after the memory information has been written in the OTPROM 4a.

Second Embodiment

A semiconductor logic unit according to a second embodiment will bedescribed with reference to FIG. 17 to FIG. 20.

FIG. 17 is a schematic view of a cross sectional structure of aninformation holding section of a third phase change memory deviceaccording to the second embodiment.

A basic structure of the information holding section of the third phasechange memory device is the same as the information holding section 10 bof the first phase change memory device 10 shown in the above-mentionedFIG. 3 of the above-mentioned first embodiment, but the difference isthat a high resistance barrier layer 20 with a thickness of, forexample, 10 nm or less is interposed between the phase change material11 and the first plug 15. For the high resistance barrier layer 20,oxide or nitride of Ti, Ta, Cr, Al or the like can be used.

FIG. 18 is a graph showing a relationship between electrical resistanceand a set-reset cycle of information in the third phase change memorydevice used in the OTPROM according to the second embodiment.

The third phase change memory device exhibits electrical resistance Roincluding electrical resistance of the high resistance barrier layerjust after fabricating it, so that the information holding section ismade to be in a high resistance state. When a relatively large voltage(for example, approximately 6 V) is applied to the third phase changememory device or a relatively large current is carried thereinto,breakdown of the high resistance barrier layer occurs. This breakdown isnot recovered (the insulating state is not realize again) at atemperature of, for example, approximately 200° C. Accordingly, afterthe high resistance barrier layer is once subjected to breakdown, adifference in electrical resistance between the amorphous state (highresistance Rr state) and the crystal state (low resistance Rs state) ofthe phase change material can be utilized as the memory information likethe information holding section 10 b of the above-mentioned first phasechange memory device 10. As shown in FIG. 18, since rewriting betweenthe high resistance Rr state and the low resistance Rs state can berepeated plural times, the third phase change memory device can be usedin the memory cell of the EEPROM.

After the high resistance barrier layer is subjected to breakdown, theinformation holding section is made to be always in a state (forexample, the high resistance Rr state or the low resistance Rs state isallowable) where a current passes more easily than the electricalresistance Ro including the electrical resistance of the high resistancebarrier layer. Accordingly, a difference in electrical resistance of theinformation holding section between the non-conductive state where thehigh resistance barrier layer is not subjected to breakdown and theconductive state where the high resistance barrier layer is subjected tobreakdown can be utilized as the memory information like the informationholding section 18 b of the above-mentioned second phase change memorydevice 18. When this usage is adopted, electric writing can be conductedonly one time, but the memory information can be held, for example,after mounting on the IC card. Accordingly, the third phase changememory device can be used in the memory cell of the OTPROM.

FIG. 19 is a sectional view of a principal part of a semiconductorsubstrate showing the third phase change memory device and theperipheral circuit low withstand voltage system nMIS used in the OTPROMaccording to the second embodiment.

A basic structure of the third phase change memory device isapproximately the same as that of the second phase change memory device18 shown in the FIG. 5 of the above-mentioned embodiment, and isconfigured by selection nMIS and an information holding section.However, the difference is that the high resistance barrier layer 20 isinterposed between the phase change material 11 and the first plug 15 ofthe information holding section, as described above. The circuitconfiguration of the OTPROM using the third phase change memory devicemay be the same as the circuit configuration of the OTPROM 4 a shown inthe above-mentioned FIG. 2 and FIG. 3 of the first embodiment.

FIG. 20 shows a block diagram of an integrated circuit of thesemiconductor logic unit according to the second embodiment. Here, forexample, RAM is formed in a volatile memory device formation region, butthe third phase change memory device is formed in a non-volatile memorydevice formation region without previously making discrimination betweenEEPROM, ROM, and OTPROM. If necessary, the high resistance barrier layer20, which is on a portion of the non-volatile memory device formationregion, is subjected to breakdown, whereby the phase change memorydevice of OTPROM or the phase change memory device of EEPROM can beprovided, for example.

As described above, according to the second embodiment, an electricallyrewritable non-volatile memory device is configured by EEPROM, and anelectrically non-rewritable non-volatile memory device is configured byOTPROM. The third phase change memory device which can be fabricated inthe same step at a low cost is used in both of the EEPROM and theOTPROM. Whereby, as with the first embodiment, the semiconductor logicunit in which the electrically rewritable non-volatile memory device andthe electrically non-rewritable non-volatile memory device are mountedon the same substrate can be fabricated at a low cost.

In the foregoing, the invention made by the present inventors has beenconcretely described based on the embodiments. However, it is needlessto say that the present invention is not limited to the above-mentionedembodiments and may be modified variously without departing from thegist of the invention.

For example, in the embodiment, a region on which OTPROM is formed and aregion on which EEPROM is formed are separately provided, but OTPROM maybe formed in the region on which EEPROM is formed, if necessary.

INDUSTRIAL APPLICABILITY

The semiconductor device of the present invention can be utilized in asemiconductor logic unit including a non-volatile memory device mountedon an IC card or an embedded micro controller.

1. A semiconductor device comprising, on the same semiconductorsubstrate, an electrically rewritable first non-volatile memory device,and an electrically non-rewritable second non-volatile memory device,wherein the first non-volatile memory device is configured by a firstphase change memory device capable of rewriting memory informationplural times, and the second non-volatile memory device is configured bya second phase change memory device capable of writing memoryinformation only one time, and information holding sections of the firstand second phase change memory devices have the same structure.
 2. Thesemiconductor device according to claim 1, wherein the memoryinformation of the first phase change memory device is rewritten bycarrying a current into a phase change material.
 3. The semiconductordevice according to claim 1, wherein the memory information of thesecond phase change memory device is written by carrying a relativelylarge current into the phase change material or applying a relativelylarge voltage thereto to disconnect the phase change material.
 4. Thesemiconductor device according to claim 1, wherein the first phasechange memory device uses an amorphous state and a crystal state of aphase change material for the memory information, and the second phasechange memory device uses a non-disconnection state and a disconnectionstate of a phase change material for the memory information.
 5. Thesemiconductor device according to claim 4, wherein by carrying arelatively large current into the phase change material of the secondphase change memory device or applying a relatively large voltagethereto, a cavity is formed in the phase change material to make thephase change material of the second phase change memory device to be inthe disconnection state.
 6. The semiconductor device according to claim1, wherein the first phase change memory device further includes a firstselection device of a low withstand voltage system functioning as aswitch, and the second phase change memory device further includes asecond selection device of a high withstand voltage system functioningas a switch.
 7. The semiconductor device according to claim 6, whereinthe first and second selection devices are a field effect transistor, abipolar transistor, or a diode.
 8. The semiconductor device according toclaim 1, wherein the first and second phase change memory devices have ahigh resistance barrier layer stacked on a phase change material, andthe high resistance barrier layers of all of first phase change memorydevices are subjected to breakdown.
 9. The semiconductor deviceaccording to claim 8, wherein the memory information of the second phasechange memory device is written by carrying a relatively large currentinto the phase change material or applying a relatively large voltagethereto to breakdown the high resistance barrier layer
 10. Thesemiconductor device according to claim 8, wherein the first phasechange memory device uses, for the memory information, an amorphousstate and a crystal state of the phase change material, and the secondphase change memory device uses, for the memory information, anon-conductive state where the high resistance barrier layer is notsubjected to breakdown and a conductive state where the high resistancebarrier layer is subjected to breakdown.
 11. The semiconductor deviceaccording to claim 8, wherein the first phase change memory devicefurther includes a first selection device of a low withstand voltagesystem functioning as a switch, and the second phase change memorydevice further includes a second selection device of a high withstandvoltage system functioning as a switch.
 12. The semiconductor deviceaccording to claim 11, wherein the first and second selection devicesare a field effect transistor, a bipolar transistor, or a diode.
 13. Thesemiconductor device according to claim 1, further comprising aprocessing unit, and a volatile memory device.
 14. A fabrication methodof a semiconductor device, comprising the steps of: (a) forming, by aunit of one chip over a semiconductor wafer, a first field effecttransistor having a relatively short gate length in a first region onwhich an electrically rewritable first non-volatile memory device isformed, and a second field effect transistor having a relatively longgate length in a second region on which an electrically non-rewritablesecond non-volatile memory device is formed; (b) forming respectivephase change materials electrically connected to drain regions of thefirst and second field effect transistors, forming a first phase changememory device comprising the first field effect transistor and the phasechange material in the first region, and forming a second phase changememory device comprising the second field effect transistor and thephase change material in the second region; (c) inspecting asemiconductor device including the first non-volatile memory device andthe second non-volatile memory device by a unit of one chip over thesemiconductor wafer, and simultaneously writing memory information inthe second phase change memory device; (d) cutting the semiconductorwafer into individual chips; and (e) rewriting memory information of thefirst phase change memory device after mounting the chip on a mountingsubstrate.
 15. The fabrication method of a semiconductor deviceaccording to claim 14, wherein in the step (c), the memory informationis written in the second phase change memory device by carrying arelatively large current into the phase change material or applying arelatively large voltage thereto to disconnect the phase change materialof the second phase change memory device.
 16. The fabrication method ofa semiconductor device according to claim 14, wherein a high resistancebarrier layer with a thickness of 10 nm or less is formed at a lowerportion of the phase change material.
 17. The fabrication method of asemiconductor device according to claim 16, wherein in the step (c), thememory information is written in the second phase change memory deviceby carrying a relatively large current into the phase change material orapplying a relatively large voltage thereto to breakdown the highresistance barrier layer.
 18. The fabrication method of a semiconductordevice according to claim 14, wherein in the step (e), the memoryinformation of the first phase change memory device is rewritten bycarrying a current into the phase change material.
 19. The fabricationmethod of a semiconductor device according to claim 14, wherein anamorphous state and a crystal state of the phase change material of thefirst phase change memory device are used for the memory information.